1. Field of the Invention
The present invention relates to a novel organosilicon polymer, more particularly, it relates to polysilphenylenesiloxanes. The present invention also relates to a process for the production of such an organosilicon polymer. Further, the present invention relates to a resist material, especially a resist material useful as the top layer resist in a bi-level resist system, and a process for the formation of resist patterns and a process for the production of semiconductor devices using such resist material. Furthermore, the present invention relates to a semiconductor device containing an interlevel dielectric, heat-resisting protective layer or other layers consisting of the novel organosilicon polymer of the present invention, and a process for the production of such a semiconductor device.
The organosilicon polymers of the present invention have a high sensitivity to ionizing radiations such as deep ultraviolet (UV) rays, electron beams (EB) or X-rays, exhibit a high contrast (for example, .gamma.=2.8), low swelling upon development (for example, 0.2 .mu.ml/s at EB), and a high softening point or temperature of 400.degree. C. or more, and accordingly, a high resolution, and further show a high resistance to oxygen (O.sub.2)-plasma etching (for example, 100 times better than that of the conventional novolak resist), and thus the organostlicon polymers of the present invention can be advantageously utilized as the resist in the production of semiconductor devices and other devices.
Moreover, since these organosilicon polymers have a high thermal resistance, a superior dielectric or electrically insulating property and a good levelling function, these organosilicon polymers can be advantageously utilized in particular in the process of the formation of multilayer wiring during the production of semiconductor devices such as integrated circuits (ICs), large-scale integrated circuits (LSIs) and ultra-large-scale integrated circuits (ULSIs). For example, if these polymers are used to form an interlevel dielectric in the production of multilayer wiring of semiconductor devices having a high integration density, such as ICe or LSIs, these polymers can be effectively spun-coated with a levelling of the underlying steps, to thereby form a layer having a superior dielectric property, and accordingly can remarkably increase the reliability of the resulting devices.
2. Description of the Related Art
A thin-film formation technology and photolithography are widely utilized in the production of electronic circuit devices with fine circuit patterns, for example, semiconductor devices, magnetic bubble memory devices and surface wave filter devices, and as an example thereof, the present description is of a production of wiring patterns. Namely, an electrically conductive layer, electrically insulating layer or other thin layers are formed on a substrate by conventional physical methods such as vacuum deposition or sputtering, or conventional chemical methods such as chemical vapor deposition (CVD), and after the formation of one thin layer, another thin layer is coated by a spin-coating method, for example, to form a resist coating. The resist coating is then pattern-wise exposed to radiations such as ultraviolet (UV) rays, and then developed to form resist patterns. Subsequent to the formation of resist patterns, the underlying thin layer is wet-etched or dry-etched, using the resist patterns as a masking means. Conductive fine patterns, insulating fine patterns or other fine patterns are formed on the substrate depending upon a specific property of the thin layer.
As an alternative, an electron beam exposure may be used to form resist patterns. Namely, after the formation of an electron beam-sensitive resist coating, an electron beam having a reduced beam diameter is scanned over the resist coating to conduct a direct pattern-wise exposure of the coating. The EB-exposed resist coating is then developed with a suitable developer, and superior fine resist patterns are thus obtained.
The above-described formation of wiring patterns is carried out on a single-layer resist system, but this system is not suitable for the production of recently developed semiconductor devices because, in the process for the production of recent semiconductor devices such as very-large-scale integrated circuits (VLSIs) or ULSIs, to increase a degree of integration of the circuits, conventionally the wiring is constituted as multilayer wiring, and as a result, step portions having a height of 1 to 2 .mu.m are formed on a surface of the substrate. This formation of the stepped portions is a bar to the obtaining of fine resist patterns with a high accuracy. Note, the single-layer resist system can not remove this bar.
To solve the problem due to the stepped portions on the substrate surface, a bi-level resist system was developed, and is now widely utilized in the production of VLSIs, ULSIs and other devices. Generally, the bi-level resist system is carried out in the manner outlined in the accompanying drawings FIGS. 1A to 1D.
FIG. 1A is a cross-sectional view of the resist-coated substrate. This system is started by coating an organic resin at a layer thickness of, for example, 2 .mu.m, on a substrate 1, such as semiconductor substrate, with a step portion 2 such as a metallic wiring, whereby a bottom layer resist (levelling layer) 3 is formed over the substrate 1. After levelling an uneven surface of the substrate 1, a resist material having a sensitivity to exposure radiations is coated at a layer thickness of about 0.2 to 0.3 .mu.m on the bottom layer resist 3, to form a top layer resist 4, and accordingly, a bi-level resist structure shown in FIG. 1A is obtained.
After the formation of the bi-level resist structure, as illustrated in FIG. 1B, the top layer resist 4 is pattern-wise exposed to exposure radiations (e.sup.-). The exposure radiations used herein are, for example, ionizing radiations such as electron beams. The exposed area of the top layer resist 4 is solubilized or insolubilized depending upon a specific property (i.e., positive-working or negative-working) of the resist 4.
Since the top layer resist 4 used herein is a negative-working resist, after development of the exposed top layer resist 4 with a selected developer 4, as shown in FIG. 1C, a pattern of the top layer resist 4 is formed over the bottom layer resist 3.
After the patterning of the top layer resist, using the pattern of this resist as a masking means, the underlying bottom layer resist is selectively etched with an etching source such as oxygen plasma. As a result, as shown in FIG. 1D, the pattern of the upper layer resist 4 is transferred to the bottom layer resist.
In the above-described bi-level resist system, since the bottom layer resist can prevent an undesirable influence of the steps of the underlying substrate on the patterning, and a reflection of exposing radiations by the substrate surface, and further, the top layer resist can be used at a reduced layer thickness, it becomes possible to remarkably increase the resolution of the resist in comparison with the single-layer resist system. The top layer resist must have a high resistance to oxygen plasma, in addition to the good sensitivity and resolution required in the single-layer resist system. The resist materials satisfying these three requirements are already known, and typical examples thereof include negative-working, organosilicone-based resist materials having a high resistance to oxygen plasma, for example, polysiloxanes having a ladder structure or phenyl ring-containing polysiloxanes. Note, as described hereinafter, both the ladder-type polysiloxanes and the phenyl-containing polysiloxanes are widely-used as the top layer resist in the bi-level resist system.
As a typical example of the ladder-type polysiloxanes used as the top layer resist, there can be mentioned the pattern-forming material described in Fukuyama et al., U.S. Pat. No. 4,863,833. The described pattern-forming material consists of polysilsesquloxane having no hydroxyl group in its molecule, the polysilsesquloxane being a silylated polysilsesquloxane of the formula: ##STR1## in which
R.sub.1 and R.sub.2 are the same or different and each represents a substituted or unsubstituted alkyl group, a substituted or unsubstituted aryl group, or a substituted or unsubstituted vinyl group, and
m is a positive integer in the approximate range of 25 to 4,000. The pattern-forming material has many advantages, such as high sensitivity to high energy radiations, good resistance to dry etching, a high resolution and thermal stability, but must be improved in the contrast and swelling thereof.
In addition, as a typical example of the phenyl-containing polysiloxanes used as the top layer resist, there can be mentioned the pattern-forming material described in European Patent Application No. 84101686.8 (Publication 0122398,A2). This pattern-forming material is characterized by containing a siloxane polymer having the general formula: ##STR2## [wherein R, R' and R" are the same or different and are respectively one member selected from the group consisting of hydrogen, an alkyl group and a phenyl group; X is one member selected from the group consisting of fluorine, chlorine, bromine, iodine and a --CH.sub.2 Y group (wherein Y is one member selected from the group consisting of chlorine, fluorine, bromine, iodine, an acryloxyloxy group, a methacryloyloxy group, and a cinnamoyloxy group); and l, m and n are respectively O or a positive integer, l and m not being simultaneously O]. Since they have a high sensitivity to high energy radiations and a good resistance to dry etching, as in the ladder-type polysiloxanes, the phenyl-containing polysiloxanes are, for example, commercially available as the "SNR" resist from Toso Corporation. Nevertheless, since they have a low sensitivity to ultraviolet rays, exhibit a large swelling upon development, and show a low contrast or gamma (.gamma.) value (for example, .gamma.=1.2 to 1.6 for the SNR resist), it is difficult to clearly resolve a narrow space pattern such as that sandwiched between wide line patterns in the formation of line and space patterns. Especially, such a difficulty is increased if the desired space pattern is very fine and has a width of 0.5 .mu.m or less. To contribute to the fine fabrication of the VLSIs and increase through-put, there is a need for the provision of an improved high resolution resist material having a high sensitivity and resistance to oxygen plasma, exhibiting less swelling upon development, and showing a high contrast.
The organosilicon polymer can be used for other purposes, in addition to the use thereof as a resist, For example, it is well-known that a silicon-containing polymer having a relatively low molecular weight produced by hydrolyzing tetraalkoxysilane and condensation-polymerizing the hydrolyzed product, i.e., inorganic SOG (spin-on-glass), is an organosilicon polymer useful in the production of semiconductor devices, and the production of such an SOG is well-known. Further, it is well-known that such an SOG can be used as an interlevel dielectic in semiconductor devices having a multilayer wiring structure.
The interlevel dielectic is essentially positioned in the semiconductor devices having a multilayer wiring structure, because two or more wiring layers of the devices must be electrically insulated from each other. The interlevel dielectric is generally produced by applying a dielectric layer onto the previously formed first wiring layer. After application of the dielectric layer, to ensure an electrical connection between the upper and lower wiring layers, throughholes are formed in the dielectric layer. Next, through this dielectric layer, a second wiring layer is formed. The above steps for the formation of the interlevel dielectric are repeated to complete a desired multilayer wiring structure. Currently, many types of the materials are used as the interlevel dielectric-providing material, and typical examples of such interlevel dielectric-providing materials include inorganic materials such as silicon dioxide, silicon nitride and phosphosilicate glass (PSG) (produced through a vapour phase deposition from reaction gases such as silane gas and oxygen gas), polymeric insulating materials such as polyimide or silicone resin, or a laminate of these materials. Nevertheless, the fine fabrication of wiring patterns is still progressing, and thus there is a need for the provision of an even more improved interlevel dielectric-providing material, to thereby increase the reliability of the resulting devices.
In the multilayer wiring, a surface of the semiconductor substrate supporting a first wiring layer has many concaves and convexes due to the presence of the wiring, and when an interlevel dielectric is formed from, for example, inorganic materials such as SiO.sub.2, over this wiring layer-supporting substrate, the resulting interlevel dielectric exactly reproduces the concaves and convexes of the underlying substrate. These concaves and convexes on the substrate surface may cause disconnections, an insufficient insulation, and other defects in the wiring formed over the underlying substrate. Therefore, a need arose for the development of an electrically insulating material which can level the concaves and convexes of the substrate, when applied over the substrate.
To satisfy the above requirement, two methods were suggested. In one method, a levelled surface of the interlevel dielectric is obtained by using a specific production process of the insulating layer such as an etching back method or bias sputtering method, and in another method a levelled surface is obtained by spin-coating the selected resin. The resin coat method is most preferable, because it is the simplest of the two processes, and further, the process of this resin coat method is simplified if the resin is not baked immediately after spin-coating, but is baked after spin-coating and a formation of throughholes for communicating the upper and lower wiring layers. Unfortunately, conventionally used resins or polymeric insulating materials such as polyimide or silicon resin are not suitable for such a simplified process, because it includes a thermal processing under elevated temperature conditions of 400.degree. C. and more, and when subjected to the temperature of 400.degree. C. or more, the conventional resins are often oxidized or thermally decomposed, or are cracked, since a distortion is induced in the resulting interlevel dielectric due to the oxidation or decomposition of the same, or other causes. Therefore, there is a need for the provision of an improved heat-resistant resinous material which is not affected by the thermal processing.
In addition, the interlevel dielectric should have a low dielectric constant. Namely, if the interlevel dielectric has a low dielectric constant it becomes possible to shorten a delay time of the wiring and thereby provide a high-speed device. Unfortunately, conventionally used inorganic materials such as SiO.sub.2, Si.sub.3 N.sub.4 and PSG have a high dielectric constant of 4.0 or more, and therefore, such high dielectric constant must be reduced. On the other hand, the inorganic SOG provides a product having a composition similar to that of SiO.sub.2 upon thermal processing, and therefore, it is difficult to obtain a reduced dielectric constant.